OZ1KLK

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(last edit: 24. september 2012)

Component

A component is analogous to a chip socket; it gives an indirect way to use one hierarchical block within another. A component is instantiated within an architecture, and is associated with a (lower level) entity and architecture during elaboration using information from a configuration.

Syntax

  component ComponentName [is]
    [Generic;]
    [Port;]
  end component [ComponentName];

Placement

 PACKAGE Pack IS
   ... 
 END PACKAGE Pack;

 PACKAGE BODY Pack IS
   ...
 END PACKAGE BODY Pack;

 Blk:BLOCK 
   ... 
 BEGIN 
   ...
 END BLOCK Blk;

 ENTITY Ent IS
   ...
 BEGIN 
   ...
 END ENTITY Ent;

 ARCHITECTURE Arc OF Ent IS
   ... 
 BEGIN 
   ...
 END ARCHITECTURE Arc;

 CONFIGURATION Conf OF Ent IS
   ... 
 END CONFIGURATION Conf;

 Proc:PROCESS(...) 
   ...
 BEGIN 
   ...
 END PROCESS Proc;

 PROCEDURE P(...) IS
   ...
 BEGIN 
   ...
 END PROCEDURE P;

 FUNCTION F(...) RETURN Tp IS
   ...
 BEGIN
   ...
 END FUNCTION F;

Rules

For default configuration, the component name must match the name of the corresponding entity to be used in its place, and generics and ports must also match in name, mode and type.

Synthesis

A component without a corresponding design entity is synthesized as a black box.

Tips

In VHDL'93, components are not necessary. It is possible instead to directly instantiate an entity within an architecture.

Example

  component Counter
    generic (
      N      : INTEGER
    );
    port (
      Clock  : in Std_logic;
      Reset  : in Std_logic;
      Enable : in Std_logic;
      Q      : buffer Std_logic_vector (N-1 downto 0)
    );
  end component;