Instantiation
A concurrent statement used to define the design hierarchy by making a copy
of a lower level design entity within an architecture. In VHDL'93, a direct
instantiation of an entity bypasses the component and configuration.
Syntax
InstanceLabel: [component] ComponentName
[GenericMap] [PortMap];
InstanceLabel: entity EntityName[(ArchitectureName)]
[GenericMap] [PortMap];
InstanceLabel: configuration ConfigurationName
[GenericMap] [PortMap];
Where
architecture-begin--end
block-begin--end
generate-begin--end
Rules
An entity, architecture or configuration must be compiled into a library before
the corresponding instance can be compiled. However, an instance of a
component can be compiled before the corresponding design entity has even
been written.
Tips
EntityName (or ConfigurationName) usually takes the form of a selected
name, because the identifier is not directly visible by default (see example).
Example
G1: NAND2 generic map (1.2 NS) port map (N1, N2, N3);
G2: entity WORK.Counter(RTL) port map (Clk, Rst, Count);
See Also
Generic map, Port map, Component, Entity, Architecture, Configuration
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