Port
A port represents a pin or a related group of pins on a hardware component,
and is defined in an entity. Technically, a port is a signal.
Syntax
port (PortName, ... : [Mode] DataType [:= Expression];
...);
Mode = {either} in out inout buffer linkage
Where
entity-is-generic(-);--begin-end
component-generic(-);--end
block-generic map(-);--port map-begin-end
Rules
In ports can only be read, out ports can only be assigned. Inout ports are
bidirectional. Buffer ports are outputs.
The Expression gives the default value for the port, and must be static. An
input port with no default value must appear in the corresponding port map.
Things to remember
You cannot read the value of an out port within an architecture.
A buffer port cannot be connected to an in or out port of the design entity
containing the instantiation; it can be connected to a buffer of that design
entity.
Tips
Do not put ports in test bench entities.
Outputs can be out ports or buffer ports. Buffer must be used when the
value of the port is to be read inside the architecture, and out must be used
when there is more than one driver for the signal.
Linkage ports cannot be read or assigned, so are not typically used.
Example
port (Clock, Reset: in Std_logic;
Q: buffer Std_logic_vector(7 downto 0);
Status: out Std_logic_vector);
See Also
Entity, Component, Port Map, Block, Generic
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