Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Array

A data type which consists of a vector or a multi-dimensional set of values of the same base type. Can be used to describe RAMs, ROMs, FIFOs, or any regular multi-dimensional structure.

Syntax

  type NewName is               {unconstrained}
    array (IndexTypeName range <>, ...) of DataType;

  type NewName is               {constrained}
    array (Range, ...) of DataType;

Placement

 PACKAGE Pack IS
   ... 
 END PACKAGE Pack;
 PACKAGE BODY Pack IS
   ... 
 END PACKAGE BODY Pack;
 Blk:BLOCK 
   ... 
 BEGIN 
   ... 
 END BLOCK Blk;
 ENTITY Ent IS
   ... 
 BEGIN 
   ... 
 END ENTITY Ent;
 ARCHITECTURE Arc OF Ent IS
   ... 
 BEGIN 
   ... 
 END ARCHITECTURE Arc;
 CONFIGURATION Conf OF Ent IS
   ... 
 END CONFIGURATION Conf;
 Proc:PROCESS(...) 
   ... 
 BEGIN 
   ... 
 END PROCESS Proc;
 PROCEDURE P(...) IS
   ... 
 BEGIN 
   ... 
 END PROCEDURE P;
 FUNCTION F(...) RETURN Tp IS
   ... 
 BEGIN
   ... 
 END FUNCTION F;

Rules

The base type DataType must not be an unconstrained array type. A signal or variable cannot be an unconstrained array, unless it is a generic, port or parameter.

Synthesis

Some synthesis tools do not support multi-dimensional arrays, only support arrays of bits or arrays of vectors, or do not permit ports to be arrays of arrays.

Tips

Large arrays should be variables or constants, rather than signals. A large signal array would be inefficient for simulation. The values within an array can be read or written using an indexed name or a slice name.

Example

  subtype Word is Std_logic_vector(15 downto 0);
  type Mem is array (0 to 2**12-1) of Word;
  variable Memory: Mem := (others => Word'(others=>'U'));
  ...
  if MemoryRead then
    Data <= Memory(To_Integer(Address));
  elsif MemoryWrite then
    Memory(To_Integer(Address)) := Data;
  end if;

See Also

Range, Name, String, Type