Click here to return to the VHDL Reference Guide. | (last edit: 24. september 2012) | |
NameAny VHDL "thing" is identified by its name. A selected name is commonly used to pick an item out of a library or package. An indexed name is used to pick an individual item out of an array. A slice name is used to pick out part of an array.SyntaxIdentifier \ExtendedIdentifier\ "Operator" Name.Name. ... {selected name} Name(Expression, ...) {indexed name} Name(Range) {slice name} AttributeName RulesAn identifier consists of letters, digits and underscores. The first character must be a letter. The last character must not be an underscore, nor can a name contain two adjacent underscores.An extended identifier consists of any printable characters. One name cannot have more than one meaning at any particular point in the VHDL text, with the exception of procedures, functions and enumeration literals, which may be overloaded. Inner declarations of names hide outer declarations. Things to rememberThe direction (i.e. to or downto) of the range in a slice name must be consistent with the subtype of the thing being sliced; otherwise it is a null range, i.e. an array of length zero.TipsGenerally, choose names which are meaningful to the reader. However, this is more important for global names than for local names. For example, G0123 is a bad name for a global reset signal, but I is an acceptable name for a loop parameter.ExampleA_99_Z -- Identifier \$%^&*()\ -- Extended identifer "+" -- Operator IEEE.STD_LOGIC_1164."nand" -- Selected name RecordVariable.ElementName -- Selected name Vector(7) -- Indexed name Matrix(I, J, K) -- Indexed name Vector(23 downto 16) -- Slice name Vector(J to K) -- Slice name Clock'EVENT -- Attribute name See AlsoAttribute Name, Operator, Expression, Range, Array, Record |