VHDL Reference Guide

Contents

• Introduction
• Using this Guide
• A Brief Introduction to VHDL - The Main Differences Between VHDL'87 and VHDL'93
• Alphabetical Reference

Introduction

The VHDL Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design.

The VHDL Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, this Reference guide does not offer a complete, formal description of VHDL. Rather, it offers answers to the questions most often asked during the practical application of VHDL, in a convenient reference format.

Nor is The VHDL Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start.

The main feature of The VHDL Reference Guide is that it embodies much practical wisdom gathered over many VHDL projects. It does not only provide a handy syntax reference; there are many similar books which perform that task adequately. It also warns you of the most common language errors, gives clues where to look when your code will not compile, alerts you to synthesis issues, and gives advice on improving your coding style.

Using this Guide

The main body of this guide is organised alphabetically. Each section is indexed by a key term which appears prominently at the top of each page. Often you can find the information you want by flicking through the guide looking for the appropriate key term. If that fails, there is a full index at the back.

Most of the information in this guide is organised around the VHDL syntax headings, but there are additional special sections on Coding Standards, Design Flow, Errors, Reserved Words and VHDL 93, and also listings of the standard packages Standard, TEXTIO, Std_logic_1164 and Numeric_std.

If you are new to VHDL, you should start by reading A Brief Introduction to VHDL.

The Index

Bold index entries have corresponding pages in the main alphabetical reference section. The remaining index entries are followed by a list of appropriate page references in the main alphabetical reference section, given in order of importance.

Key To Notation Used To Define VHDL Syntax

The syntax in this reference guide describes VHDL'93. The main differences between VHDL'87 and VHDL'93 can be found here.

The syntax definitions are written using the Backus-Naur-format.

Here follows a short summary of the format:

• Words written using lower-case letters and possibly one or many hyphens, are used to denote a syntactical category, for example: entity-declaration.
• Reserved words are written with bold characters, for example: entity.
• Every replacement rule contains a left hand side expression and a right hand side expression separated by the sign ûø, which means ölooks asö or ömay be replaced withö. The left hand side of the expression is always a syntactical category and may be replaced by the right hand side of the expression.
• |, a vertical line (the pipe sign) is used to separate many mutually exclusive alternatives.
• [], square brackets surround optional things that may occur once or not at all.
• {}, braces surround optional things that may occur once, many times or not at all.
• (), parenthesis are used to clarify how and in which order a rule is evaluated.
• Reserved words and characters surrounded by apostrophes, æ Æ, are included öas isö in the source code.
• Italicized words in the beginning of the name of a syntactical category give semantic information and have no syntactical meaning. For example entity-name-identifier is the same as identifier.

In brief, square brackets [ ] enclose optional items, three dots ... means repetition, and curly brackets { } enclose comments. ItalicNames represent parts of the syntax defined elsewhere. A full description of the notation follows:

• Curly brackets { } enclose comments that are not part of the VHDL syntax being defined, but give you further information about the syntax definition.
• Syntax enclosed in square brackets [ ] is optional (except in the definition of a signature, where square brackets are part of the VHDL syntax!)
• ... means zero or more repetitions of the preceding item or line, or means a list, as follows:
• Item ... means zero or more repetitions of the Item.
• , ... means repeat in a comma separated list (e.g. A, B, C).
• ; ... means repeat in a semicolon separated list (e.g. A;B;C).
• | ... means repeat in a bar separated list (e.g. A|B|C).

There must be at least one item in the list. There is no , ; or | at the end of the list, unless it is given explicitly (as in ; ... ; ).

Underlined syntax belongs to the VHDL'93 language, but not to VHDL'87. (For the sake of clarity, underlining has been omitted where words contain the underscore character.) words in lower case letters are reserved words, built into the VHDL language (e.g. entity)

Capitalised Words (not in italics) are VHDL identifiers, i.e. user defined or pre-defined names that are not reserved identifiers (e.g. TypeName, BlockLabel).

Italic Words are syntactic categories, i.e. the name of a syntax definition given in full elsewhere. A syntactic category can be either defined on the same page, defined on a separate page, or one of the two special categories defined below.

• Italics = indicates a syntactic category which is defined and used on the same page.

Special syntactic categories:

• SomethingExpression = Expression, where the Something gives information about the meaning of the expression (e.g. TimeExpression).
• Condition = Expression, where the type of the expression is Boolean.

A Brief Introduction to VHDL -

The Main Differences Between VHDL'87 and VHDL'93

The most essential differences between VHDL'87 and VHDL'93 are described below.

Syntax

VHDL'93 has a more symmetric syntax, especially for the conclusion of composite statements and the five design units. Below follow examples of conclusions different in the two versions of the standard (note that the VHDL'87 syntax is permitted also in VHDL'93):

VHDL'87	VHDL'93
end entity_name;	end entity entity_name;
end arch_name;	end architecture arch_name;
end pck_name;	end package pck_name;
end pck_name;	end package body pck_name;
end conf_name;	end configuration conf_name;
end component;	end component comp_name;
end fn_name;	end function fn_name;
end proc_name;	end procedure proc_name;
end record;	end record rec_name;

Below follow examples where the start of statements differ:

 blk_name:block 

 blk_name:block is 

 proc_name:process 

 proc_name:process is 

 component comp_name 

 component comp_name is 

Above the previous examples VHDL'93 permits labeling of all statements.
Composite statements may then use the label also at the end of the statement, for example:

  Control:IF a > b THEN
    ...
  END IF Control;

That is not permitted in VHDL'87.

GENERATE

The GENERATE statement (see page 45) has in VHDL'93 been enhanced with a declarational part and has also been raised to a block with a local scope. The GENERATE statement in VHDL'87 does not have a declarational part. It is however possible to write code compatible with both standards by avoiding the declarational part and by putting a BLOCK statement within the GENERATE statement.

Concurrent signal assignment

Conditional concurrent signal assignments (see page 41) must in VHDL'87 have an concluding ELSE condition. The reserved word UNAFFECTED, that is new to VHDL'93, was included to be able to leave a signal unaffected during an assignment, i.e. to keep its previous value:

  a <= b WHEN s = '1' ELSE a;  --VHDL'87 requires a concluding ELSE
  a <= b WHEN s = '1';  -- Works in VHDL'93
  a <= b WHEN t = "00" ELSE  -- Works in VHDL'93
  UNAFFECTED WHEN t = "01" ELSE
  c; 

Files

The handling of files differ quite a lot between VHDL'87 and VHDL'93 (see page 19-21). Most changes are not backwards compatible. Below follow examples of the different versions of file declarations:

  -- VHDL'87:
  FILE f1:my File IS IN"name_in_file_system";
  FILE f2:my SecondFile IS OUT"name_in_file_system";

  --VHDL'93:
  FILE f1:myFile OPEN READ_MODE IS "name_in_file_system";
  FILE f2:mySecondFile OPEN WRITE_MODE IS "name_in_file_system";

Input files may be written in VHDL code compatible with both VHDL'87 and VHDL'93, but for output files that is not possible:

  -- Declaration of an input file both for VHDL'87 and VHDL'93
  FILE f:myFile IS "name_in_file_system";

The predefined subprograms FILE_OPEN and FILE_CLOSE does not exist in VHDL'87.

File parameters for subprograms do not have a mode in VHDL'93 as they do in VHDL'87. Input files for subprograms may be written in VHDL code compatible with both VHDL'87 and VHDL'93:

  -- Subprogram with a file parameter for both VHDL'87 and VHDL'93
  PROCEDURE ReadFile(FILE f:myFile; value : OUT INTEGER);

Functions using files outside their local scope must in VHDL'93 be declared as IMPURE. IMPURE does not exist in VHDL'87.

Character set

The character set in VHDL'93 (see page 7, 56-57) is completely ISO 8859-1 : 1987(E) compatible and includes 256 characters. The character set in VHDL'87 is limited to the first 128 characters and does not include international characters, not even in comments. Many VHDL'87 tools do however support international charactersr in comments.

Extended identifiers

VHDL'93 permits the usage of extended identifiers. An extended identifier always starts and ends with a `\' (backslash) and may include for example spaces and reserved words. Note that extended identifiers are case sensitive.

Shared variables

VHDL'93 permits shared variables (see page 17) in concurrent declaration statements.

Impure functions

An impure function does not only work via its parameters and may therefore return different values with identical input parameters. A function calling an impure function, or a procedure with side-effects (a procedure not only working via its parameters), must be declared as impure. The function NOW, that returns current simulation time, is an impure function in VHDL'93. All functions utilizing NOW must therefore be declared as impure.

Direct instantiation

In VHDL'93 it is permitted to exclude the component declaration and directly instantiate an ENTITY or a CONFIGURATION DECLARATION. This is called direct instantiation (see pages 46, 47). In VHDL'87 a component declaration is needed.

Port associations

In VHDL'93 it is permitted to have a constant value as actual parameter for an input port in a parameter association list (see pages 47-50). In VHDL'87 an actual parameter must be a signal.

VHDL'93 does also permit, above type conversion functions, that direct type conversion (type conversion functions between closely related types) is used between formal and actual parameters (see pages 43, 44, 47). In VHDL'93 it is also possible to have a slice as formal parameter.

Attributes

A number of new attributes (see pages 51-55) are added to VHDL'93. They are `ASCENDING, `IMAGE, `VALUE, `DRIVING, `DRIVING_VALUE, `SIMPLE_NAME, `INSTANCE_NAME and `PATH_NAME.

The lack of the attribute `IMAGE in VHDL'87 may be quite annoying and one must write functions that convert values to text strings. In some cases it is possible to utilize STD.TEXTIO.READ and STD.TEXTIO.WRITE to create such functions, at least for the predefined types:

  FUNCTION INTEGER_IMAGE(i:INTEGER) RETURN STRING IS
    USE STD.TEXTIO.ALL;

    --Determines the number of characters in the string
    FUNCTION length(i:INTEGER) RETURN NATURAL IS
      VARIABLE l   : LINE;
      VARIABLE tmp : NATURAL;
    BEGIN
      WRITE(l,i);
      tmp := l'LENGTH;
      DEALLOCATE(l);  --Remove the line pointer
      RETURN tmp;
    END FUNCTION length;

    VARIABLE st : STRING(1 TO length(i));
    VARIABLE l  : LINE;
    BEGIN
      WRITE(l,i);
    st := l.ALL;
    DEALLOCATE(l);  -- Remove the line pointer
    RETURN st;
  END FUNCTION INTEGER_IMAGE;

The attributes `STRUCTURE and `BEHAVIOR were removed to VHDL'93.

  REPORT

The REPORT statement is new to VHDL'93. In VHDL'87 it is possible to utilize REPORT in combination with ASSERT:

  ASSERT FALSE REPORT "...";

Signal delay mechanisms

INERTIAL is new to VHDL'93 and is used to express an inertial delay (see page 37). In VHDL'93 it is possible to combine INERTIAL and TRANSPORT in a signal assignment using REJECT. That is not possible in VHDL'87 and an extra signal is needed to obtain the same functionality:

  --VHDL'93:
  a <= REJECT 2ns INERTIAL b AFTER 5ns;
  --VHDL'87:
  tmp <= b AFTER 2ns;
  a <= TRANSPORT tmp AFTER 3ns; 

Delayed concurrent statements

In VHDL'93 it is possible to declare all concurrent statements active during simulation (see pages 38-42) as POSTPONED which means that they are executed as the final delta at a specific occasion. VHDL'87 does not have that functionality and there are no tricks to manually create it.

Alias

In VHDL'87 aliases (see page 22) may be declared only for objects, while it in VHDL'93 is possible to declare aliases also for subprograms, operators, types and for all named entities except "labels", "loop parameters" and "generate parameters".

Bit string literals

In VHDL'87 a bit string literal is always of the type BIT_VECTOR. In VHDL'93 the bit string literals have been generalized to be an alternative way to write an aggregate of any array type whose elements can have the values `0' or `1'.

  -- Permitted in VHDL'93
  LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    ...
  SIGNAL s : STD_LOGIC_VECTOR(0 TO 15);
  ...
  s <= x"A1B0";

Unfortunately this generalization may arise ambiguousnesses when overloaded subprograms are used. The assignment above should be written like this in VHDL'87:

  s <= TO_STDLOGICVECTOR(x"A1B0");

This will however result in a compilation error in VHDL'93 since the bit string literal fits many different array types, and it is therefore not possible for the compiler to determine which of all conversion functions named TO_STDLOGICVECTOR to use.

The following line works fine both for VHDL'87 and for VHDL'93:

  s <= TO_STDLOGICVECTOR(BIT_VECTOR'(x"A1B0"));