Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Range

A range specifies a range of values belonging to an integer, floating, physical or enumeration type. A static range is one whose bounds can be calculated during compilation or elaboration.

Syntax

  {either}
  Expression to Expression
  Expression downto Expression
  Name'RANGE                                   {name of an array or array type} 
  Name'REVERSE_RANGE
  DataType                                     {enumeration or integer type}
    

Placement

 PACKAGE Pack IS
   ... 
 END PACKAGE Pack;
 PACKAGE BODY Pack IS
   ... 
 END PACKAGE BODY Pack;
 Blk:BLOCK 
   ... 
 BEGIN 
   ... 
 END BLOCK Blk;
 ENTITY Ent IS
   ... 
 BEGIN 
   ... 
 END ENTITY Ent;
 ARCHITECTURE Arc OF Ent IS
   ... 
 BEGIN 
   ... 
 END ARCHITECTURE Arc;
 CONFIGURATION Conf OF Ent IS
   ... 
 END CONFIGURATION Conf;
 Proc:PROCESS(...) 
   ... 
 BEGIN 
   ... 
 END PROCESS Proc;
 PROCEDURE P(...) IS
   ... 
 BEGIN 
   ... 
 END PROCEDURE P;
 FUNCTION F(...) RETURN Tp IS
   ... 
 BEGIN
   ... 
 END FUNCTION F;

Rules

The values of the Expressions must be consistent with the direction of the range. E.g. 0 downto 7 is a null range, of length 0.

Tips

Any form of range can be used in a for loop or an index constraint. Use the 'RANGE form of range in preference to Expression to Expression where possible, as this often makes the code easier to maintain.

Example

  subtype INT is INTEGER range 0 to 7;
  subtype V1 is STD_LOGIC_VECTOR(INT);
  subtype V2 is INTEGER range V1'REVERSE_RANGE;
  ...
  for I in V2 range 3 downto 0 loop
    ...
    

See Also

Data Type, Subtype, Integer, Floating, Attribute Name