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HDL Reference GuideContents
IntroductionThis HDL Reference Guide is a combined quick reference guide to the VHDL language, the Verilog Language and the SystemVerilog Language its syntax, semantics, synthesis and application to hardware design. This Reference Guide shows examples of all three languages and compares the different ways of constructing the functionality. It is not intended as a replacement for the IEEE Standard HDL Language Reference Manuals. Unlike these documents, this Reference guide does not offer a complete, formal description of HDL. Rather, it offers answers to the questions most often asked during the practical application of HDL, in a convenient reference format. Nor is The HDL Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start. The main feature of The HDL Reference Guide is that it compiles information regarding VHDL, Verilog and SystemVerilo into an easy to use page with examples and comparisons to aide the HDL designer working in shifting environments and shifting languages. Using this Guide |
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Active Package Actual After And Anonymous Ascending Base Based Literal Binary Concatenation Bit Bit_Vector Body Boolean Buffer Bus Call Character Choice Clock Close Combinational Logic Composite Concurrent Signal Assignment Condition Constrained Array Constraint Constraint Violation Context Clause Conversion Function If Decimal Attribute Name Declarative Region Delay Delayed Delta Textio Design Entity Design Unit Don't Care Driver Finite State Machine Driving Elaboration Else Elsif Endfile Event Examples Exponent Expression Extended Identifier Falling_Edge File (Vhdl) Flipflop For Name Foreign Formal Process Guarded Hexadecimal High Attribute Name Identifer Image Impure In Incomplete Assignment Incomplete Type Index Constraint Indexed Name Indication Inertial Initialization Inout Input Instance_Name Last_Active Last_Event Last_Value Latch Left Variable Length Octal Library Unit Line Linkage Literal Low Mod Mode Nand Natural Nor Generate Now Entity Object Open Or Others Out Output Overloading Package Body Parameter Passive Process Path_Name Pitfalls Pos Positive Report Postponed Reset Precedence Coding Standards Pred Data Type Process Pure Quiet Read Real Register Transfer Level Register Reject Rem Resolution Reverse_Range Right Rising_Edge Rol Ror Selected Name Sensitivity List Severity Signature Signed Simple_Name Select Simulation Cycle Sla Slice Sll Speed Of Simulation Sra Srl Stable Static Std Std_Logic Std_Match Subprogram Use Succ Target Test Bench Time To_Integer Transaction Transport Unaffected Unconstrained Array Units Unsigned Until Val Value Visibility When With Work Write Xnor Xor
Access Type Aggregate Alias Allocator Architecture Array Assertion Statement Attributes (predefined) Attributes (user-defined) Bit Bit_Vector Block Statement Boolean Case Statement Character Type Component Declaration Component Instantiation Composite Type Concatenation Configuration Declaration Configuration Specification Constant Delay Driver Entity Enumeration Type Event Exit Statement Expression File Declaration File Type Floating Point Type Function Generate Statement Generic Group Guard Identifier If Statement Integer Type Library Clause Literal Loop Statement Name Next Statement Null Statement Operator Overloading Operators Package Package Body Physical Type Port Procedure Process Statement Range Record Type Report Statement Reserved Word Resolution Function Resume Return Statement Scalar Type Sensitivity List Signal Assignment Signal Declaration Slice Standard Package Std_Logic Std_Logic_1164 Package Std_Logic_Vector String Subtype Suspend Testbench Type Type Conversion Use Clause Variable Assignment Variable Declaration Vector VITAL Wait Statement Waveform