Package
A package contains common definitions that can be shared across a VHDL
design or even several designs. A package is split into a declaration and a
body. The package declaration defines the external interface to the package,
the package body typically contains the bodies of any functions or procedures
defined in the package declaration.
Syntax
{declaration}
package PackageName is
Declarations...
end [package] [PackageName];
{body}
package body PackageName is
Declarations...
end [package body] [PackageName];
Where
See (VHDL) File
Tips
Common, shared declarations of types, subtypes, constants, procedures,
functions and components are best put in a package.
Things to remember
Where a function or procedure is placed in a package, the declaration and
body must conform, i.e. the parameters must be identical between the two.
Only definitions placed in the package declaration are visible outside the
package.
Example
(See Function)
library IEEE;
use IEEE.Std_logic_1164.all;
package UTILITIES is
-- Declarations...
subtype Byte is Std_logic_vector(7 downto 0);
function PARITY (V: Byte) return Std_logic;
end UTILITIES;
package body UTILITIES is
-- Bodies...
function PARITY (V: Byte) return Std_logic is
variable B: Std_logic := '0';
begin
for I in V'RANGE loop
B := B xor V(I);
end loop;
return B;
end PARITY;
end UTILITIES;
See Also
(VHDL) File, Use, Function, Procedure, Declaration, Type, Component
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