Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Attribute

A user defined attribute is used to attach arbitrary information to a specific part of a VHDL description for use by downstream tools (e.g. synthesis or device fitting). Any attribute not recognized by a particular tool is ignored. Each attribute must be both declared and specified as shown below.

Syntax

  {declaration}
  attribute AttributeName: TypeName;

  {specification}
  attribute AttributeName of Name [Signature]: Class is
                                               Expression;
   Signature = [TypeName, ...] return TypeName
  Class = {either} signal type function architecture {etc}

Where

See Declaration
An attribute specification must be in the region in which the Name is declared. Attributes of an entity, architecture, configuration or package must be specified inside that region. Neither attribute declaration nor specification is allowed in a Package Body.

Rules

Name Signature may be replaced by others, all, or a list. A procedure, function or enumeration literal must be identified unambiguously by a Signature, which identifies the parameter types and return type (to allow for overloading).

Example

  attribute Pin_number: Positive;
  attribute Pin_number of Clk: signal is 1;
  attribute Enum_encoding: String;
  attribute Enum_encoding of State: type is "11 00 01 10";

See Also

Attribute Name, Group