VHDL Math Tricks

Introduction

• VHDL Types & Packages
• Strong Typing Rules
• Converting between Std_logic_vector, unsigned & signed
• Ambiguous Expressions
• Arithmetic Coding Considerations
• Math Tricks

Common VHDL Types

Packages for Numeric Operations

• numeric_std -- IEEE standard
• Defines types signed, unsigned
• Defines arithmetic, comparison, and logic operators for these types

• std_logic_arith -- Synopsys, a defacto industry standard
• Defines types signed, unsigned
• Defines arithmetic, and comparison operators for these types

• std_logic_unsigned -- Synopsys, a defacto industry standard
• Defines arithmetic and comparison operators for std_logic_vector

Using IEEE Numeric_Std

  library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

Using Synopsys Std_Logic_Arith

  library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

Unsigned and Signed Types

• Used to represent numeric values:

• Usage similar to std_logic_vector:

  signal A_unsigned : unsigned(3 downto 0);
  signal B_signed : signed (3 downto 0);
  signal C_slv : std_logic_vector (3 downto 0);
    . . .
  A_unsigned <= "1111"; -- = 15 decimal
  B_signed <= "1111";   -- = -1 decimal
  C_slv <= "1111";      -- = 15 decimal only if using std_logic_unsigned 

• Type definitions identical to std_logic_vector

  type UNSIGNED is array (natural range <>) of std_logic; 
  type SIGNED is array (natural range <>) of std_logic; 

• How are the types distinguished from each other?
• How do these generate unsigned and signed arithmetic?
• For each operator, a unique function is called

  function "+" (L, R: signed) return signed; 
  function "+" (L, R: unsigned) return unsigned; 

• This feature is called Operator Overloading:
• An operator symbol or subprogram name can be used more than once as long as calls are differentiable.

Overloading Basics

• Simplified view of overloading provided by VHDL packages

• For a detailed view of VHDL's overloading, get the VHDL Types and Operators Quick Reference card at: http://www.SynthWorks.com/papers

Overloading Examples

  Signal A_uv, B_uv, C_uv, D_uv, E_uv : unsigned(7 downto 0);
  Signal R_sv, S_sv, T_sv, U_sv, V_sv : signed(7 downto 0);
  Signal J_slv, K_slv, L_slv : std_logic_vector(7 downto 0);
  signal Y_sv : signed(8 downto 0);
    ...

  -- Permitted
  A_uv <= B_uv + C_uv ; -- Unsigned + Unsigned = Unsigned
  D_uv <= B_uv + 1 ; -- Unsigned + Integer = Unsigned
  E_uv <= 1 + C_uv; -- Integer + Unsigned = Unsigned

  R_sv <= S_sv + T_sv ; -- Signed + Signed = Signed
  U_sv <= S_sv + 1 ; -- Signed + Integer = Signed
  V_sv <= 1 + T_sv; -- Integer + Signed = Signed

  J_slv <= K_slv + L_slv ; -- if using std_logic_unsigned

  -- Illegal Cannot mix different array types
  -- Solution presented later in type conversions
  -- Y_sv <= A_uv - B_uv ; -- want signed result 

Strong Typing Implications

• Size and type of target (left) = size and type of expression (right)
• Each operation returns a result that has a specific size based on rules of the operation. The table below summarizes these rules.

  Operation              Size of Y = Size of Expression 
  Y <= "10101010";       number of digits in literal 
  Y <= X"AA";            4 * (number of digits) 
  Y <= A;                A'Length = Length of array A 
  Y <= A and B;          A'Length = B'Length 
  W <= A > B;            Boolean 
  Y <= A + B;            Maximum (A'Length, B'Length) 
  Y <= A + 10;           A'Length 
  V <= A * B;            A'Length + B'Length 

Strong Typing Implications

  signal A8, B8, Result8 : unsigned(7 downto 0);
  signal Result9         : unsigned(8 downto 0);
  signal Result7         : unsigned(6 downto 0);
  ...

  -- Simple Addition, no carry out
  Result8 <= A8 + B8;

  -- Carry Out in result
  Result9 <= ('0' & A8) + ('0' & B8);

  -- For smaller result, slice input arrays
  Result7 <= A8(6 downto 0) + B8(6 downto 0); 

Type Conversions

• VHDL is dependent on overloaded operators and conversions
• What conversion functions are needed?
  • Signed & Unsigned (elements) <=> Std_Logic
  • Signed & Unsigned <=> Std_Logic_Vector
  • Signed & Unsigned <=> Integer
  • Std_Logic_vector <=> Integer
• VHDL Built-In Conversions
• Automatic Type Conversion
• Conversion by Type Casting
• Conversion functions located in Numeric_Std

Automatic Type Conversion: Unsigned, Signed <=> Std_Logic

• Two types convert automatically when both are subtypes of the same type

subtype std_logic is resolved std_ulogic;

• Converting between std_ulogic and std_logic is automatic

• Elements of Signed, Unsigned, and std_logic_vector = std_logic
• Elements of these types convert automatically to std_ulogic or std_logic

Legal Assignments

A_sl <= J_uv(0); B_sul <= K_sv(7); L_uv(0) <= C_sl; M_slv(2) <= N_sv(2);




Implication:

Y_sl <= A_sl and B_sul and J_uv(2) and K_sv(7) and M_slv(2);

Type Casting: Unsigned, Signed <=> Std_Logic_Vector

• Use type casting to convert equal sized arrays when:
  • Elements have a common base type (i.e. std_logic)
  • Indices have a common base type (i.e. Integer)

• Unsigned, Signed <=> Std_Logic_Vector

A_slv <= std_logic_vector( B_uv ); C_slv <= std_logic_vector( D_sv ); G_uv <= unsigned( H_slv ); J_sv <= signed( K_slv );

• Motivation, Unsigned - Unsigned = Signed?

signal X_uv, Y_uv : unsigned (6 downto 0); signal Z_sv : signed (7 downto 0); . . . Z_sv <= signed('0' & X_uv) -signed('0' & Y_uv);

Numeric_Std Conversions: Unsigned, Signed <=> Integer

• Converting to and from integer requires a conversion function.
• Unsigned, Signed => Integer

Unsigned_int <= TO_INTEGER ( A_uv ); Signed_int <= TO_INTEGER ( B_sv );

• Integer => Unsigned, Signed

C_uv <= TO_UNSIGNED ( Unsigned_int, 8 ); D_sv <= TO_SIGNED ( Signed_int, 8 );

Array width = 8

• Motivation (indexing an array of an array):

Data_slv <= ROM( TO_INTEGER( Addr_uv) );

 signal A_uv, C_uv : unsigned (7 downto 0);
 signal Unsigned_int : integer range 0 to 255 ; 
 signal B_sv, D_sv : signed( 7 downto 0) ; 
 signal Signed_int : integer range -128 to 127; 

Std_Logic_Arith Conversions: Unsigned, Signed <=> Integer

• Converting to and from integer requires a conversion function.
• Unsigned, Signed => Integer

Unsigned_int <= Conv_INTEGER ( A_uv ); Signed_int <= Conv_INTEGER ( B_sv );

• Integer => Unsigned, Signed

C_uv <= Conv_UNSIGNED ( Unsigned_int, 8 ); D_sv <= Conv_SIGNED ( Signed_int, 8 ); Array width = 8

• Motivation (indexing an array of an array):

Data_slv <= ROM( Conv_INTEGER( Addr_uv) );

 signal A_uv, C_uv : unsigned (7 downto 0);
 signal Unsigned_int : integer range 0 to 255;
 signal B_sv, D_sv : signed( 7 downto 0);
 signal Signed_int : integer range -128 to 127;

Std_Logic_Vector <=> Integer

Ambiguous Expressions

Std_Logic_Arith: Ambiguous Expressions

Addition Operators